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NJU3426
16-SEGMENT X 14-Digit VFD CONTROLLER / DRIVER
GENERAL DESCRIPTION
The NJU3426 is a VFD (Vacuum Fluorescent Display) controller/driver to dynamically drive up to 16 segments x 14 digits. It consists of display data RAM, an address counter, command registers, a serial interface and high voltage drivers. The NJU3426 features the direct connection to MPU and the high voltage drivers of 45V well-suited for various VFD displays.
PACKAGE OUTLINE
NJU3426FP1
FEATURES
Directly Drives 16-segment x 14-digit High VFD Driving Voltage : |VDD-VFDP|45V Display Shift Function Programmable Duty Ratio for Timing Signal :2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16 duty Display ON/OFF Control Function Display Data RAM : 30 x 8-bit Built-in Oscillator (External Ceramic Resonator or External Resistor or External Clock) 8-bit Serial Interface Power-ON Reset Function Operating Voltage : 3.3V / 5.0V C-MOS Technology Package Outline :QFP48-P1
BLOCK DIAGRAM
S0 to S15
T0 to T13
VDD VSS VFDP
High Voltage Driver
High Voltage Driver
Segment Data Latch
Timing Counter
Address Counter
Character Address Counter
Display RAM 30 x8-bit
Initial Character Address Counter
Duty Counter
Timing Counter
OSC Instruction Decoder
XT XTb
SI SCK CSb
Serial Buffer
REST
RSTb
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NJU3426
PIN CONFIGURATION
N.C. 26 N.C. N.C. T13 T12 T11 T10 T9 T8 T7 T4 N.C. 25 24 23 22 21 T6 29 T5 28
38
37
36
35
34
33
32
31
30
VFDP N.C. RSTb CSb SCK SI VSS XT XTb VDD
27
39 40 41 42 43 44 45 46 47 10 12 13 11 48 1 2 3 4 5 6 7 8 9
T3 T2 T1 T0 S15 S14 S13 S12 S11 S10
NJU3426FP1
20 19 18 17 16 14 N.C. 15
S0
S1
S2
S3
S4
S5
S6
S7
S8
N.C.
N.C.
S9
TERMINAL DISCRIPTION
PAD No. 48 45 39 46 47 SYMBOL VDD VSS VFDP XT XTb FUNCTION Power Supply For Logic Voltage 3.3V / 5.0V Ground VSS=0V Power Supply For VFD Driving Voltage Ceramic Resonator Connection, Resistor Connection, or External Clock Input The internal oscillator is formed by connecting an external ceramic resonator to these pins. When an external oscillator is used instead of the internal oscillator, the external clock is input to the XT and the XTb must be open. Segment output terminals (Pulled down) Timing output terminals (Pulled down) Reset terminal (Pulled up) Active "L": Reset is executed when this pin is "L". Reset does not change the contents of display data RAM. Chip Select Active "L": Data transmission is enable when this pin is "L". Serial Clock Input Serial Data Input (8 bits = 1 word) Non connections These pins must be open.
3 to 12, 15 to 20 21 to 24, 27 to 36 41
S0 to S15 T0 to T13 RSTb
42 43 44 1, 2, 13, 14, 25, 26, 37, 38, 40
CSb SCK SI N.C.
N.C.
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NJU3426
FUNCTION DESCRIPTION
(1) ADDRESS COUNTER The address counter specifies the "Display data RAM address", and the display data is transferred to or from this address. For the data transmission, once an initial RAM address is determined, the display data can be continuously transmitted without setting the RAM address. When the upper 2 bits (B7 and B6) of the 1st word are "0,0", the lower 5 bits (B4 to B0) are interpreted as RAM address data. And the 2nd word is interpreted as display data which is stored in the RAM address specified by the 1st word, and simultaneously the RAM address is counted up. Although the "Display data RAM address" can be set only in the range of "0,0,0,0,0" (00H) and "1,1,1,0,1" (1DH), the auto-increment keeps counting up to "1,1,1,1,1" (1FH), and the RAM address finally wraps to "0,0,0,0,0" (00H) then begins counting up. Note that the display data, specified to the RAM address of "1,1,1,1,0" (1EH) or "1,1,1,1,1" (1FH), is ignored in this sequence. DISPLAY DATA RAM ADDRESS B7 0 B6 0 B5 * B4 AD4 B3 AD3 B2 AD2 B1 AD1 B0 AD0
Recognition data
Display data RAM address *:don't care
Character address
B7
B6
B5
B4
B3
B2
B1
B0
RAM Address
B7
B6
B5
B4
B3
B2
B1
B0
RAM Address
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 S15 S14 S13 S12 S11 S10 S9 S8
01H 03H 05H 07H 09H 0BH 0DH 0FH 11H 13H 15H 17H 19H 1BH 1DH 1FH S7 S6 S5 S4 S3 S2 S1 S0
00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH
: Non-existent Address DISPLAY DATA RAM MAP
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NJU3426
(2) COMMAND REGISTER 1 The "Command register 1" is used for setting "Duty ratio for timing signal", "Display control ON/OFF" and "Shifting display digits". When the upper 1 bit (B7) of the 1st word is "1", the lower 7 bits (B6 to B0) are interpreted as command data, and stored in the "Command register 1". The contents of the "Command register 1" are initialized to the default values by the power-ON reset or the reset signal, as shown below. DEFAULT VALUES OF COMMAND REGISTER 1 * Duty ratio for timing signal : 2/16 * Display control ON/OFF : OFF * Shifting display digits :7 B7 1 B6 DT2 B5 DT1 B4 DT0 B3 DSP B2 DE2 B1 DE1 B0 DE0
Recognition data
Duty ratio for timing signal
Display control ON / OFF
Shifting display digits
Note.)
DT2 DT1 DT0 Duty ratio for timing signal 0 0 0 2/16 0 0 1 4/16 0 1 0 6/16 0 1 1 8/16 1 0 0 10/16 1 0 1 12/16 1 1 0 14/16 1 1 1 15/16 The output waveforms of timing signal are shown in " TIMING SIGNAL / DUTY-CHANGE WAVEFORM". DSP Display control 0 OFF 1 ON When the "Display control OFF" is set, segment drivers output waveforms but all timing signal outputs are halted DE2 0 0 0 0 1 1 1 1 DE1 0 0 1 1 0 0 1 1 DE0 0 1 0 1 0 1 0 1 Shifting display digits 7 8 9 10 11 12 13 14
Note.)
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NJU3426
(3) COMMAND REGISTER 2 The "Command register 2" is used for setting the "Initial character address", which corresponds to the T0 pin. When the upper 2 bits (B7 and B6) of the 1st word is "0,1", the lower 4 bits (B3 to B0) are interpreted as command data and stored in the "Command register 2". The contents of the "Command register 2" are initialized to the default values by the power-ON reset or the reset signal, as shown below. DEFAULT VALUES OF COMMAND REGISTER 2 * Initial character address : C1 (0,0,0,1) B7 0 B6 1 B5 * B4 * B3 DS3 B2 DS2 B1 DS1 B0 DS0
Recognition data
Initial character address *:don't care
DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Initial character address C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Prohibited
Ver.2003-09-02
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NJU3426
(4) DISPLAY SHIFT OPERATION The display shift operation is performed by changing the "Initial character address" of the "Command register 2". And the number of digits for the display shift in the loop is determined by the "Shifting display digits" of the "Command register 1". In other words, shifting display area ranges from the "Initial character address" specified by the "Command register 2" to the last address specified by the "Command register 1". The default value of the "Initial character address" is C1 (0,0,0,1), as shown in the table of "Display data RAM". In addition, supposing that the value of the "Shifting display digits" is "N", the "Initial character address" should be set in the range of C0 and CN in order not to exceed the digit "N". Because the display shift operation is not applied to the addresses beyond the digit "N", the display images, which were initially set up, appear on these addresses. Just for reference, one character of display image is composed of 16 segments. HOW TO SET LEFT DISPLAY SHIFT The left display shift is carried out by incrementing the "Initial character address" gradually like C2, C3, C4, --- CN. To the contrary, decrementing the address performs right display shift. The following description shows the example on how to set the left display shift, using alphanumeric display images such as "0", "1", "2", ---, "9", "A", "B", ---, and "E". STEP1) Setting display images in the display data RAM
*
Display RAM data Character address Display image
C0 0
C1 1
C2 2
C3 3
C4 4
C5 5
C6 6
C7 7
C8 8
C9 C10 C11 C12 C13 C14 9 A B C D E
SETP2) Setting the "Initial character address" to C2 and the "Shifting display digits N" to 12 (T11). Shifting display digits
Character address Timing output terminals Character Display image
C1
C2
C3
C12
C0
C13
C14
T0 1
T1 2
T10 11
T11 12
T12 13
T13 14
is not shifted. In this setting, the display images of "2", "3",- - - appear on the T0, T1, T2, - - - T10 pins respectively, and the image "0" is on the T11 pin, which is assigned to the 12th character address. The display images "D" and "E" don't shift but remain on the T12 and T13 pins, assigned to the 13th and 14th characters respectively, because their character addresses are outside the digit "N". STEP3) Changing the "Initial character address" to C3, and leaving the "Shifting display digits N" as 12 (T11). Shifting display digits
Character address Timing output terminals Character Display image
C2
C3
C4
C0
C1
C13
C14
T0 1
T1 2
T10 11
T11 12
T12 13
T13 14
is not shifted.
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Ver.2003-09-02
NJU3426
TIMING SIGNAL / DUTY-CHANGE WAVEFORM
Display timing
13 14 15 DT2 DT1 DT0 01 2345 678 9 10 11 12 13 14 15 01 2 3 456
(Duty count)
2/16 4/16 6/16 8/16 10/16 12/16 14/16 15/16
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Timing signal (T0 to T13)
Segment signal
DISPLAY TIMING CHART
fXT XT tBK T0 T1 T2 * * * * T13 tSP * * * * tDG
S0 to S15
Oscillation frequency Minimum blanking time (duty15/16) 1-character display time 1-cycle display time
: fXT : tBK=(1/fXT) x 16 x 2 : tDG=tBK x 16 : tSP=tDG x 14
:800kHz to 3.5MHz :40s to 9.14s :640s to 146.28s :8.96ms to 2.05ms
Ver.2003-09-02
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NJU3426
(5) SERIAL DATA TRANSMISSION Communication between the NJU3426 and MPU uses the serial data transmission with synchronous clock, and 8 bits serial data constitutes 1 word. Each bit on the SI pin is latched at the rising edge of the serial clock (SCK), and the entire 8 bits are loaded as 1 word at the rising edge of the chip select (CSb). During a data transmission, multiple words are transferred continuously. The 1st word is either "Display data RAM address", "Command register 1" or "Command register 2". When the 1st word is RAM address data, the 2nd and ascending words are interpreted as display data. When it's the "Command register 1 or 2", the 2nd and ascending words are ignored. SCK
SI
D0
D1
D2
D3
D4
D5
D6
D7
SERIAL DATA TIMING
CSb
SCK WORD n
SI
WORD 1
WORD 2
SERIAL DATA TRANSMISSION FORMAT
*
Serial input data ST DATA FORMAT FOR THE 1 WORD DISPLAY DATA RAM ADRESS B7 0 B6 0 B5 * B4 AD4 B3 AD3 B2 AD2 B1 AD1 B0 AD0 *:don't care COMMAND DATA 1 B7 1 B6 DT2 B5 DT1 B4 DT0 B3 DSP B2 DE2 B1 DE1 B0 DE0 *:don't care COMMAND DATA 2 B7 0 B6 1 B5 * B4 * B3 DS3 B2 DS2 B1 DS1 B0 DS0 *:don't care
ND
SERIAL DATA FOR THE 2 AND ASCENDING WORDS When the 1st word is the "Display data RAM address", the 2nd and ascending words are interpreted as display data. When the 1st word is the "Command register 1 or 2", the 2nd and ascending words are ignored.
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NJU3426
ABSOLUTE MAXIMAM RATINGS
PARAMETER Supply voltage Input voltage VFD driving voltage "H" level output current 1 "H" level output current 2 "L" level output current Operating temperature Storage temperature Power dissipation Note 1): Note 2): Note 3): SYMBOL VDD VIN VFDP IOH1 IOH2 IOL Topr Tstg PD RATINGS -0.3 to +7.0 -0.3 to VDD+0.3 VDD-45 to VDD+0.3 -15 -35 20 -40 to 85 -55 to 125 1500 UNIT V V V mA mA mA C C mW (VSS=0V, Ta=25C) CONDITIONS
Relative to VDD. 1 pin out of S0 to S15 pins 1 pin out of T0 to T13 pins
The LSI must be used inside the "Absolute maximum ratings". cause a permanent damage to the LSI. De-coupling capacitors should be placed on VDD and VSS and VFDP and VSS for stable operation. The following voltage relation must be maintained; VDD> VSS VFDP, VSS=0.
On two-layer board of based on the JEDEC. Otherwise, an electrical or physical stress may
Ver.2003-09-02
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NJU3426
ELECTRICAL CHARACTERISTICS
*
DC characteristics 1 (VDD=5.0V, VSS=0V, Ta=-40 to 85C) MIN TYP MAX UNIT 4.5 5.5 V 0.8VDD V 0.2VDD 1 -4.5 -10.5 100 60 -9 -21 280 160 A mA mA k k
PARAMETER SYMBOL CONDITIONS Operating voltage VDD VDD terminal XT, RSTb, CSb, SCK, SI terminals "H" level input voltage VIH "L" level input voltage VIL CSb, SCK, SI terminals Input off leak current IIZ VDD=5.5V, VI=0 or 5.5V SO to S15 VDD=4.5V, terminals VFDP=VDD-40V, Display output current IOH VOH=VDD-2.5V TO to T13 terminals Pull-up resistance RUR RSTb terminal, Ta=25C, VI=VSS S0 to S15, T0 to T13 terminals, Ta=25C Pull-down resistance RDST VI=VDD, VFDP=VDD-40V VSS terminal, All Segment/Timing output terminals open, RSTb terminal open, Logic operating current ISS Ceramic resonator:1MHz, All Segment output OFF and All Timing output OFF VFDP terminal, VFDP=VDD-40V, Display operating IFDP Ceramic resonator:1MHz, current All Segment/Timing output ON
1
2
mA
10
15
mA
*
AC characteristics 1 SYMBOL fXT fCR tCLH, tCLL tSIS tSIH fSCK tSCI tRSTb tR CONDITIONS Fig. 1 Ta=25C Rf=27k Fig. 2 Fig. 2 Fig. 2 Fig. 3 Fig. 3 Fig. 4 Fig. 5 35 35 1.5 10 10 0.05 (VDD=5.0V, VSS=0V, Ta=-40 to 85C) MIN TYP MAX UNIT 0.8 3.5 MHZ 0.85 1 1.15 250 *) MHz ns ns ns MHZ s s ms
PARAMETER Operating oscillation frequency CR oscillation frequency * External clock Input Rise time, Fall time Serial input data setup time Serial input data hold time Serial clock frequency Serial clock interval time Reset palse width Power rise time
10
*) Noises on SCK during rise time or fall time may cause malfunctions. Testing samples in the application is recommended.
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Ver.2003-09-02
NJU3426
*
DC characteristics 2
(VDD=3.3V, VSS=0V, Ta=-40 to 85C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating voltage VDD VDD terminal 3.0 3.6 V XT, RSTb, CSb, SCK, SI terminals "H" level input voltage VIH 0.8VDD V "L" level input voltage VIL 0.2VDD CSb, SCK, SI terminals Input off leak current IIZ 1 A VDD=3.6V, VI=0 or 3.6V VDD=3.0V, S0 to S15 -2 -4 mA terminals VFDP=VDD-40V, Display output current IOH VOH=VDD-1.5V T0 to T13 -4.5 -9 mA terminals Pull-up resistance RUR RSTb terminal, Ta=25C, VI=VSS 100 280 k S0 to S15, T0 to T13 terminals, Ta=25C 60 160 Pull-down resistance RDST k VI=VDD, VFDP=VDD-40V VSS terminal, All Segment/Timing output terminals open, RSTb terminal open, 0.8 1.5 mA Logic operating current ISS Ceramic resonator:1MHz, All Segment output OFF and All Timing output OFF VFDP terminal, VFDP=VDD-40V, Display operating Ceramic resonator:1MHz, 10 15 mA IFDP current All Segment/Timing output ON
*
AC characteristics 2 SYMBOL fXT fCR tCLH, tCLL tSIS tSIH fSCK tSCI tRSTb tR CONDITIONS Fig. 1 Ta=25C Rf=18k Fig. 2 Fig. 2 Fig. 2 Fig. 3 Fig. 3 Fig. 4 Fig. 5 70 70 0.8 10 20 0.05 (VDD=3.3V, VSS=0V, Ta=-40 to 85C) MIN TYP MAX UNIT 0.8 2 MHZ 0.85 1 1.15 250 *) MHz ns ns ns MHZ s s ms
PARAMETER Operating oscillation frequency CR oscillation frequency * External clock Input Rise time, Fall time Serial input data setup time Serial input data hold time Serial clock frequency Serial clock interval time Reset palse width Power rise time
5
*) Noises on SCK during rise time or fall time may cause malfunctions. Testing samples in the application is recommended.
Ver.2003-09-02
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NJU3426
* Relation between external resistor (Rf) and oscillation frequency (fCR). The frequency can be adjusted by the selection of external resistor Rf, as shown in "Rf vs fCR". Refer to circuit example of " APPLICATION CIRCUIT (b) CR oscillation".
Rf vs fCR
4 3
fCR [MHz]
VDD=5.0V VDD=3.0V
2
1
0 0 10 20 Rf [k] 30 40
This graph shows a reference characteristic, and this performance is not guaranteed.
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Ver.2003-09-02
NJU3426
fXT VIH XT
VIH
Fig. 1 tCLL VIH SCK VIL tSIS SI VIH VIL Fig. 2 50% VIL tSIH VIH VIL tCLH VIH
CSb
50%
SCK
50% tSCI
50% fSCK tSCI Fig. 3 tRSTb
50% tSCI
RSTb VIL VIL
Fig. 4 tR 90% VDD 10% Fig. 5
Ver.2003-09-02
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NJU3426
APPLICATION CIRCUIT
(a) Ceramic Resonator Oscillation
C0
N.C.
N.C.
N.C. N.C.
VFDP N.C. RSTb
CPU
CSb SCK SI VSS
NJU3426FP1
C1
C2 R
XT XTb N.C. N.C.
VDD C0
VFD
N.C.
VDD
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
N.C.
T13
T12
T11
T10
VFDP
T4
T6
T9
T8
T7
T5
T3
T2 T1 T0 S15 S14 S13 S12 S11 S10
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Ver.2003-09-02
NJU3426
(b) Ceramic Resonator Oscillation
C0
N.C.
N.C.
N.C. N.C.
VFDP N.C. RSTb
CPU
CSb SCK SI VSS Rf XT XTb N.C. N.C. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
NJU3426FP1
VDD C0
VFD
N.C.
VDD
N.C.
VFDP
T13
T12
T10
T11
T7
T4
T9
T8
T6
T5
T3
T2 T1 T0 S15 S14 S13 S12 S11 S10
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2003-09-02
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